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22–18
Table 22–24 shows the ROM block inputs and outputs.
Table 22–24. ROM Block Inputs and Outputs
Chapter 22: Storage Library
addr
ena
q
Signal
Direction
Input
Input
Output
Description
Input data port.
Optional clock enable port.
Output data port.
Table 22–25 shows the ROM block parameters.
Table 22–25. ROM Block Parameters
Name
Number of Words
Data Type
[number of bits].[]
[].[number of bits]
Memory Block
Type
Initialization
Input HEX File
MATLAB Array
Register output
Port
Use Enable Port
Clock Phase
Selection
DSP Builder Handbook
Value
User Defined
(Parameterizable)
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
AUTO, M512, M4K,
M9K, MLAB, M144K
From HEX file,
From MATLAB array
User defined
User defined
(Parameterizable)
On or Off
On or Off
User Defined
Description
Specify the depth of the ROM in words.
The data type format.
Specify the number of bits stored on the left side of the binary point including
the sign bit.
Specify the number of bits stored on the right side of the binary point. This
option applies only to signed fractional formats.
The RAM block type. Some memory types are not available for all device types.
Specify whether the ROM is initialized from a . hex file or from a MATLAB array.
Specify the name of a. hex file that must be in your DSP Builder working
directory. For example: input.hex .
DSP Builder supports 32-bit addressing with extended linear address records
in the .hex file.
Specify a one-dimensional MATLAB array with a length less than or equal to the
number of words. For example: [0:1:15]
Turn on to register the output port.
Turn on to use the optional clock enable input ( ena ).
Specify the phase selection with a binary string, where a 1 indicates the phase
in which the block is enabled. For example:
1 —The block is always enabled and captures all data passing through the
block (sampled at the rate 1).
10 —The block is enabled every other phase and every other data (sampled
at the rate 1) passes through.
0100 —The block is enabled on the second phase of and only the second
data of (sampled at the rate 1) passes through. That is, the data on phases 1,
3, and 4 do not pass through the delay block.
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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